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18-Bit, 1.33 MSPS PulSAR 10.5 mW ADC in MSOP/QFN AD7984
FEATURES
18-bit resolution with no missing codes Throughput: 1.33 MSPS Low power dissipation: 10.5 mW at 1.33 MSPS INL: 2.25 LSB maximum Dynamic range: 99.7 dB typical True differential analog input range: VREF 0 V to VREF with VREF between 2.9 V to 5.0 V Allows use of any input range Easy to drive with the ADA4941 No pipeline delay Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface Serial interface SPI-/QSPITM-/MICROWIRETM-/DSP-compatible Ability to daisy-chain multiple ADCs and busy indicator 10-lead MSOP (MSOP-8 size) and 10-lead 3 mm x 3 mm QFN (LFCSP), SOT-23 size
APPLICATION DIAGRAM
2.9V TO 5V 2.5V
IN+
REF VDD VIO SDI SCK SDO GND CNV
1.8V TO 5V
10V, 5V, ..
AD7984
IN-
Figure 1.
GENERAL DESCRIPTION
The AD7984 is an 18-bit, successive approximation, analog-todigital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 18-bit sampling ADC and a versatile serial interface port. On the CNV rising edge, the AD7984 samples the voltage difference between the IN+ and IN- pins. The voltages on these pins usually swing in opposite phases between 0 V and VREF. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. The SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provides an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. The AD7984 is available in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from -40C to +85C.
APPLICATIONS
Battery-powered equipment Data acquisition systems Medical instruments Seismic data acquisition systems
Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR(R) ADC
Type 14-Bit 16-Bit 100 kSPS AD7940 AD7680 AD7683 AD7684 250 kSPS AD79421 AD76851 AD76871 AD7694 AD7691 1 400 kSPS to 500 kSPS AD79461 AD76861 AD76881 AD76931 AD76901 1000 kSPS AD79801 AD79831 AD79821 AD79841 ADC Driver ADA4941-x ADA4841-x ADA4941-x ADA4841-x
18-Bit
1
Pin-for-pin compatible.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
06973-001
ADA4941
3- OR 4-WIRE INTERFACE (SPI, CS DAISY CHAIN)
AD7984 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Application Diagram........................................................................ 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 11 Theory of Operation ...................................................................... 12 Circuit Information.................................................................... 12 Converter Operation.................................................................. 12 Typical Connection Diagram ................................................... 13 Analog Inputs.............................................................................. 14 Driver Amplifier Choice ........................................................... 14 Single-to-Differential Driver .................................................... 15 Voltage Reference Input ............................................................ 15 Power Supply............................................................................... 15 Digital Interface.......................................................................... 16 CS Mode, 3-Wire Without Busy Indicator ............................. 17 CS Mode, 3-Wire with Busy Indicator .................................... 18 CS Mode, 4-Wire Without Busy Indicator ............................. 19 CS Mode, 4-Wire with Busy Indicator .................................... 20 Chain Mode Without Busy Indicator ...................................... 21 Chain Mode with Busy Indicator............................................. 22 Application Hints ........................................................................... 23 Layout .......................................................................................... 23 Evaluating the AD7984 Performance ...................................... 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24
REVISION HISTORY
11/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD7984 SPECIFICATIONS
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = -40C to +85C, unless otherwise noted. Table 2.
Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Common-Mode Input Range Analog Input CMRR Leakage Current at 25C Input Impedance ACCURACY No Missing Codes Differential Linearity Error Integral Linearity Error Transition Noise Gain Error, TMIN to TMAX 3 Gain Error Temperature Drift Zero Error, TMIN to TMAX3 Zero Temperature Drift Power Supply Sensitivity THROUGHPUT Conversion Rate Transient Response AC ACCURACY Dynamic Range Signal-to-Noise, SNR Spurious-Free Dynamic Range, SFDR Total Harmonic Distortion 4 , THD Signal-to-(Noise + Distortion), SINAD
1 2 3
Conditions
Min 18 -VREF -0.1 VREF x 0.475
Typ
Max
Unit Bits V V V dB 1 nA
IN+ - IN- IN+, IN- IN+, IN- fIN = 450 kHz Acquisition phase
VREF x 0.5 67 200 See the Analog Inputs section
+VREF VREF + 0.1 VREF x 0.525
18 -1 -2.25 -0.075 -700 VDD = 2.5 V 5% 0 Full-scale step VREF = 5 V fIN = 1 kHz, VREF = 5 V, TA = 25C fIN = 10 kHz fIN = 10 kHz fIN = 10 kHz, VREF = 5 V, TA = 25C 99.7 98.5 112.5 -110.5 98 0.95 0.022 -0.6 100 0.3 90
+1.5 +2.25 +0.075 +700
Bits LSB 2 LSB2 LSB2 % of FS ppm/C V ppm/C dB1 MSPS ns dB1 dB1 dB1 dB1 dB1
1.33 290
96.5
All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. LSB means least significant bit. With the 5 V input range, one LSB is 38.15 V. See Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 4 Tested fully in production at fIN = 1 kHz.
Rev. 0 | Page 3 of 24
AD7984
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = -40C to +85C, unless otherwise noted. Table 3.
Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS -3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 1, 2 Power Dissipation Energy per Conversion TEMPERATURE RANGE 3 Specified Performance
1 2
Conditions
Min 2.9
Typ
Max 5.1
Unit V A MHz ns
1.33 MSPS
520 10 2
VIO > 3 V VIO > 3 V VIO 3 V VIO 3 V
-0.3 0.7 x VIO -0.3 0.9 x VIO -1 -1
+0.3 x VIO VIO + 0.3 +0.1 x VIO VIO + 0.3 +1 +1
V V V V A A
ISINK = +500 A ISOURCE = -500 A
Serial 18 bits, twos complement Conversion results available immediately after completed conversion 0.4 VIO - 0.3 2.375 2.3 1.8 2.5 2.625 5.5 5.5 14
V V V V V mA mW nJ/sample C
Specified performance VDD and VIO = 2.5 V 1.33 MSPS throughput
1.1 10.5 7.9 -40
TMIN to TMAX
+85
With all digital inputs forced to VIO or GND as required. During acquisition phase. 3 Contact an Analog Devices, Inc., sales representative for the extended temperature range.
Rev. 0 | Page 4 of 24
AD7984
TIMING SPECIFICATIONS
TA = -40C to +85C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted. 1 Table 4.
Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO Above 3 V VIO Above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge SDI Valid Hold Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (Chain Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with Busy Indicator)
1
Symbol tCONV tACQ tCYC tCNVH tSCK
Min 300 250 750 10 10.5 12 13 15
Typ
Max 500
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tSCK 11.5 13 14 16 4.5 4.5 3 9.5 11 12 14 tEN 10 15 20 5 2 0 5 5 2 3 15 ns ns ns ns ns ns ns ns ns ns ns
tSCKL tSCKH tHSDO tDSDO
ns ns ns ns
tDIS tSSDICNV tHSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI
See Figure 2 and Figure 3 for load conditions.
500A
IOL
X% VIO1
Y% VIO1
tDELAY
TO SDO CL 20pF
06973-002
tDELAY
VIH2 VIL2 VIH2 VIL2
06973-003
1.4V
500A
IOH
1FOR VIO 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30. 2MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS IH IL
SPECIFICATIONS IN TABLE 3.
Figure 2. Load Circuit for Digital Interface Timing
Figure 3. Voltage Levels for Timing
Rev. 0 | Page 5 of 24
AD7984 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Analog Inputs IN+, IN- to GND 1 Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature JA Thermal Impedance 10-Lead MSOP 10-Lead QFN (LFCSP) JC Thermal Impedance 10-Lead MSOP 10-Lead QFN (LFCSP) Lead Temperatures Vapor Phase (60 sec) Infrared (15 sec)
1
Rating -0.3 V to VREF + 0.3 V or 130 mA -0.3 V to +6.0 V -0.3 V to +3.0 V +3 V to -6 V -0.3 V to VIO + 0.3 V -0.3 V to VIO + 0.3 V -65C to +150C 150C 200C/W 48.7C/W 44C/W 2.96C/W 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
See the Analog Inputs section for an explanation of IN+ and IN-.
Rev. 0 | Page 6 of 24
AD7984 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF 1 VDD 2 IN+ 3 IN- 4 GND 5 VIO SDI SCK
06973-004
REF 1 VDD 2 IN+ 3 IN- 4 GND 5
10
10 VIO
AD7984
TOP VIEW (Not to Scale)
9 8 7 6
CNV
6
CNV
Figure 4. 10-Lead MSOP Pin Configuration
Figure 5. 10-Lead QFN (LFCSP) Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 Mnemonic REF VDD IN+ IN- GND CNV Type 1 AI P AI AI P DI Description Reference Input Voltage. The REF range is 2.9 V to 5.1 V. This pin is referred to the GND pin and should be decoupled closely to the GND pin with a 10 F capacitor. Power Supply. Differential Positive Analog Input. Differential Negative Analog Input. Power Supply Ground. Convert Input. This input has multiple functions. On its rising edge, it initiates the conversions and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data should be read when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).
7 8 9
SDO SCK SDI
DO DI DI
10
1
VIO
P
AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. 0 | Page 7 of 24
06973-005
SDO
TOP VIEW (Not to Scale)
AD7984
9 8 7
SDI SCK SDO
AD7984 TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, REF = 5.0 V, VIO = 3.3 V.
2.0 1.5 1.0 0.5 POSITIVE INL: +1.07LSB NEGATIVE INL: -0.73LSB 2.0 1.5 1.0 0.5 0 -0.5 -1.0
06973-032
POSITIVE DNL: +0.63LSB NEGATIVE DNL: -0.34LSB
0 -0.5 -1.0 -1.5 -2.0
DNL (LSB)
INL (LSB)
0
65536
131072 CODE
196608
262144
-2.0
0
65536
131072 CODE
196608
262144
Figure 6. Integral Nonlinearity vs. Code
60k 60k
Figure 9. Differential Nonlinearity vs. Code
55354
50k
50k
48273
48266
40k
40k 31003
COUNTS
30k
COUNTS
32350
30k
20k
20k
16593
14653
10k 0 1C 0 1D 7 1E 326 1F
06973-041
0
326 20 21 22 23 24 25
6 26
0 27
0 28
0
0 1D
0 1E
2 1F
69 20
1801 21 22 23 24 25
1378 37 26 27
0 28
0 29
CODE IN HEX
CODE IN HEX
Figure 7. Histogram of a DC Input at the Code Center
0 -20
Figure 10. Histogram of a DC Input at the Code Transition
100 99 98 97
AMPLITUDE (dB of Full Scale)
-40 -60 -80 -100 -120 -140
SNR = 98.2dB THD = -110.6dB SFDR = 112.5dB SINAD = 98.0dB
fS = 1.33MSPS fIN = 10kHz
SNR (dB)
96 95 94 93 92
06973-033
91 90 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0
-180
0
100
200
300
400
500
600
FREQUENCY (kHz)
INPUT LEVEL (dB of Full Scale)
Figure 8. FFT Plot
Figure 11. SNR vs. Input Level
Rev. 0 | Page 8 of 24
06973-039
-160
06973-042
5992
5708
10k
06973-038
-1.5
AD7984
100 SNR 95 17 SINAD -105 18 -100
SNR, SINAD (dB)
ENOB (Bits)
90
16
THD (dB)
-110
ENOB 85 15 -115
06973-045
06973-043
80 2.5
3.0
3.5
4.0
4.5
5.0
14 5.5
-120 2.5
3.0
3.5
4.0
4.5
5.0
5.5
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage
100 -100
Figure 15. THD vs. Reference Voltage
98 -105 96
SNR (dB)
THD (dB)
06973-044
-110
94
-115 92
06973-046
90 -55
-35
-15
5
25
45
65
85
105
-120 -55
-35
-15
5
25
45
65
85
105
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 13. SNR vs. Temperature
100 -80 -85 95 -90
Figure 16. THD vs. Temperature
SINAD (dB)
90
THD (dB)
06973-034
-95 -100 -105 -110 -115
85
80
1
10 FREQUENCY (kHz)
100
1000
1
10 FREQUENCY (kHz)
100
1000
Figure 14. SINAD vs. Frequency
Figure 17. THD vs. Frequency
Rev. 0 | Page 9 of 24
06973-040
AD7984
2.5 IVDD 2.5 IVDD
OPERATING CURRENTS (mA)
1.5
OPERATING CURRENTS (mA)
2.0
2.0
1.5
1.0 IREF 0.5
06973-035
1.0 IREF 0.5
06973-037
IVIO 0 2.375
IVIO 0 -55
2.425
2.475
2.525
2.575
2.625
-35
-15
5
25
45
65
85
105
125
VDD VOLTAGE (V)
TEMPERATURE (C)
Figure 18. Operating Currents vs. Supply
1.5 1.4 1.3
Figure 20. Operating Currents vs. Temperature
STANDBY CURRENTS (mA)
1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -55 -35 -15 5 25 45 65 85 105
06973-036
IVDD + IVIO
125
TEMPERATURE (C)
Figure 19. Standby Currents vs. Temperature
Rev. 0 | Page 10 of 24
AD7984 TERMINOLOGY
Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, that is, 0 V, from the actual voltage producing the midscale output code, that is, 0 LSB. Gain Error The first transition (from 100 ... 00 to 100 ... 01) should occur at a level 1/2 LSB above nominal negative full scale (-4.999981 V for the 5 V range). The last transition (from 011 ... 10 to 011 ... 11) should occur for an analog voltage 11/2 LSB below the nominal full scale (+4.999943 V for the 5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB = (SINADdB - 1.76)/6.02 and is expressed in bits. Noise-Free Code Resolution Noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise) and is expressed in bits. Effective Resolution Effective resolution is calculated as Effective Resolution = log2(2N/RMS Input Noise) and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. It is measured with a signal at -60 dBF so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measurement of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied.
Rev. 0 | Page 11 of 24
AD7984 THEORY OF OPERATION
IN+
SWITCHES CONTROL
MSB REF GND 131,072C 65,536C 4C 2C C C
LSB
SW+
BUSY COMP CONTROL LOGIC OUTPUT CODE
131,072C
65,536C MSB
4C
2C
C
C LSB SW-
CNV
IN-
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7984 is a fast, low power, single-supply, precise, 18-bit ADC using a successive approximation architecture and is capable of converting 1,330,000 samples per second (1.33 MSPS). The AD7984 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7984 can be interfaced to any 1.8 V to 5 V digital logic family. It is available in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that allows space savings and flexible configurations. It is pin-for-pin-compatible with the 18-bit AD7982.
CONVERTER OPERATION
The AD7984 is a successive approximation ADC based on a charge redistribution DAC. Figure 21 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 18 binary-weighted capacitors, which are connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the input of the comparator are connected to GND via SW+ and SW-. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN- inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW- are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs IN+ and IN- captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/262,144). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. Because the AD7984 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.
Rev. 0 | Page 12 of 24
06973-011
AD7984
Transfer Functions
The ideal transfer characteristic for the AD7984 is shown in Figure 22 and Table 7.
ADC CODE (TWOS COMPLEMENT)
Table 7. Output Codes and Ideal Input Voltages
Description FSR - 1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR
1 2
011 ... 111 011 ... 110 011 ... 101
Analog Input VREF = 5 V +4.999962 V +38.15 V 0V -38.15 V -4.999962 V -5 V
Digital Output Code (Hex) 0x1FFFF1 0x00001 0x00000 0x3FFFF 0x20001 0x200002
This is also the code for an overranged analog input (VIN+ - VIN- above VREF - VGND). This is also the code for an underranged analog input (VIN+ - VIN- below VGND).
100 ... 010 100 ... 001 100 ... 000 -FSR
TYPICAL CONNECTION DIAGRAM
-FSR + 1 LSB
06973-012
-FSR + 0.5 LSB
+FSR - 1 LSB +FSR - 1.5 LSB
Figure 23 shows an example of the recommended connection diagram for the AD7984 when multiple supplies are available.
ANALOG INPUT
Figure 22. ADC Ideal Transfer Function
V+ V+
REF1 10F2 100nF
2.5V
1.8V TO 5V 15 0 TO VREF V-
4
100nF REF IN+ VDD VIO SDI SCK SDO IN- 3-WIRE INTERFACE
2.7nF
V+ 15 VREF TO 0 2.7nF V-
4
AD7984
GND
CNV
ADA48412, 3
Figure 23. Typical Application Diagram with Multiple Supplies
Rev. 0 | Page 13 of 24
06973-013
NOTES 1SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2C REF IS USUALLY A 10F CERAMIC CAPACITOR (X5R). SEE RECOMMENDED LAYOUT IN FIGURE 40 AND FIGURE 41. 3SEE DRIVER AMPLIFIER CHOICE SECTION. 4OPTIONAL FILTER. SEE ANALOG INPUTS SECTION.
AD7984
ANALOG INPUTS
Figure 24 shows an equivalent circuit of the input structure of the AD7984. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN-. Care must be taken to ensure that the analog input signal does not exceed the reference input voltage (REF) by more than 0.3 V. If the analog input signal exceeds this level, the diodes become forward-biased and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. However, if the supplies of the input buffer (for example, the supplies of the ADA4841 in Figure 23) are different from those of REF, the analog input signal may eventually exceed the supply rails by more than 0.3 V. In such a case (for example, an input buffer with a shortcircuit), the current limitation can be used to protect the part.
REF D1 IN+ OR IN- CPIN GND D2
06973-014
When the source impedance of the driving circuit is low, the AD7984 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency.
DRIVER AMPLIFIER CHOICE
Although the AD7984 is easy to drive, the driver amplifier must meet the following requirements:
*
RIN
CIN
The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7984. The noise from the driver is filtered by the AD7984 analog input circuit's 1-pole, lowpass filter made by RIN and CIN or by the external filter, if one is used. Because the typical noise of the AD7984 is 36.24 V rms, the SNR degradation due to the amplifier is
36.24 = 20 log 2 36.24 + f - 3dB (Ne N ) 2 2
SNR LOSS
Figure 24. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true differential signal between IN+ and IN-. By using these differential inputs, signals common to both inputs are rejected.
90
85
80
CMRR (dB)
where: f-3dB is the input bandwidth, in megahertz, of the AD7984 (10 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/Hz. * * For ac applications, the driver should have a THD performance commensurate with the AD7984. For multichannel multiplexed applications, the driver amplifier and the AD7984 analog input circuit must settle for a full-scale step onto the capacitor array at an 18-bit level (0.0004%, 4 ppm). In the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at an 18-bit level and should be verified prior to driver selection.
75
70
65
1
10
100 FREQUENCY (kHz)
1000
10000
Figure 25. Analog Input CMRR vs. Frequency
06973-015
60
During the acquisition phase, the impedance of the analog inputs (IN+ or IN-) can be modeled as a parallel combination of capacitor, CPIN, and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the sampling phase, where the switches are closed, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits noise.
Table 8. Recommended Driver Amplifiers
Amplifier ADA4941-x ADA4841-x AD8021 AD8022 OP184 AD8655 AD8605, AD8615 Typical Application Very low noise, low power single-to-differential Very low noise, small, and low power Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single supply, low noise 5 V single supply, low power
Rev. 0 | Page 14 of 24
AD7984
SINGLE-TO-DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either bipolar or unipolar, the ADA4941-x single-ended-todifferential driver allows for a differential input into the part. The schematic is shown in Figure 26. R1 and R2 set the attenuation ratio between the input range and the ADC range (VREF). R1, R2, and CF are chosen depending on the desired input resistance, signal bandwidth, antialiasing, and noise contribution. For example, for the 10 V range with a 4 k impedance, R2 = 1 k and R1 = 4 k. R3 and R4 set the common mode on the IN- input, and R5 and R6 set the common mode on the IN+ input of the ADC. The common mode should be close to VREF/2. For example, for the 10 V range with a single supply, R3 = 8.45 k, R4 = 11.8 k, R5 = 10.5 k, and R6 = 9.76 k.
R5 R3 R6 R4 +5.2V 100nF REF 10F +5V REF +2.5V REF VDD
If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 F (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. If desired, a reference-decoupling capacitor with values as small as 2.2 F can be used with a minimal impact on performance, especially DNL. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins.
POWER SUPPLY
The AD7984 uses two power supply pins: a core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 5.5 V. To reduce the number of supplies needed, VIO and VDD can be tied together. The AD7984 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 27.
95
OUTN
15 2.7nF
IN+
OUTP 100nF IN FB 15
2.7nF
AD7984
IN- GND
90 85
PSRR (dB)
06973-016
ADA4941
10V, 5V, .. R1 -0.2V R2 CF
80 75 70 65 60
Figure 26. Single-Ended-to-Differential Driver Circuit
1
10
The AD7984 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. When REF is driven by a very low impedance source (for example, a reference buffer using the AD8031 or the AD8605), a 10 F (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance.
100 FREQUENCY (kHz)
1000
Figure 27. PSRR vs. Frequency
To ensure optimum performance, VDD should be roughly half of REF, the voltage reference input. For example, if REF is 5.0 V, VDD should be set to 2.5 V (5%).
Rev. 0 | Page 15 of 24
06973-017
VOLTAGE REFERENCE INPUT
AD7984
DIGITAL INTERFACE
Although the AD7984 has a reduced number of pins, it offers flexibility in its serial interface modes. When in CS mode, the AD7984 is compatible with SPI, QSPI, digital hosts, and DSPs. In this mode, the AD7984 can use either a 3-wire or 4-wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. When in chain mode, the AD7984 provides a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high, and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected, the chain mode is always selected. In either mode, the AD7984 offers the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must timeout the maximum conversion time prior to readback. The busy indicator feature is enabled * * In CS mode if CNV or SDI is low when the ADC conversion ends (see Figure 31 and Figure 35). In chain mode if SCK is high during the CNV rising edge (see Figure 39).
Rev. 0 | Page 16 of 24
AD7984
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7984 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 28, and the corresponding timing is given in Figure 29. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. When a conversion is initiated, it continues until completion irrespective of the state of CNV. This can be useful, for example, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7984 enters the acquisition phase and goes into standby mode. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 18th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance.
CONVERT CNV VIO SDI
DIGITAL HOST
SDO DATA IN
AD7984
SCK
CLK
Figure 28. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
SDI = 1
tCYC tCNVH
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSCK tSCKL
SCK 1 2 3 16 17 18
tHSDO tEN
SDO D17 D16
tSCKH tDSDO
D15 D1 D0
06973-018
tDIS
06973-019
Figure 29. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
Rev. 0 | Page 17 of 24
AD7984
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7984 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 30, and the corresponding timing is given in Figure 31. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7984 then enters the acquisition phase and goes into standby mode. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 19th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. If multiple AD7984s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation.
CONVERT VIO CNV VIO SDI 47k
DIGITAL HOST
DATA IN IRQ CLK
06973-020
AD7984
SCK
SDO
Figure 30. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
SDI = 1
tCYC tCNVH
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSCK tSCKL
SCK 1 2 3 17 18 19
tHSDO tDSDO
SDO D17 D16
tSCKH tDIS
D1 D0
06973-021
Figure 31. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
Rev. 0 | Page 18 of 24
AD7984
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7984s are connected to an SPI-compatible digital host. A connection diagram example using two AD7984s is shown in Figure 32, and the corresponding timing is given in Figure 33. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7984 enters the acquisition phase and goes into standby mode. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 18th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance and another AD7984 can be read.
CS2 CS1 CONVERT CNV SDI CNV SDO SDI
AD7984
SCK
AD7984
SCK
SDO
DIGITAL HOST
Figure 32. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
tCYC
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSSDICNV
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK tSCKL
SCK 1 2 3 16 17 18 19 20 34 35 36
tHSDO tEN
SDO D17 D16
tSCKH tDSDO
D15 D1 D0 D17 D16 D1 D0
06973-022
DATA IN CLK
tDIS
06973-023
Figure 33. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Rev. 0 | Page 19 of 24
AD7984
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7984 is connected to an SPI-compatible digital host with an interrupt input and when it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This independence is particularly important in applications where low jitter on CNV is desired. The connection diagram is shown in Figure 34, and the corresponding timing is given in Figure 35. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. (If SDI and CNV are low, SDO is driven low.) Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7984 then enters the acquisition phase and goes into standby mode. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 19th SCK falling edge or SDI going high (whichever occurs first), SDO returns to high impedance.
CS1 CONVERT VIO CNV 47k SDI
DIGITAL HOST
DATA IN IRQ CLK
06973-024
AD7984
SCK
SDO
Figure 34. CS Mode, 4-Wire with Busy Indicator Connection Diagram
tCYC
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSSDICNV
SDI
tHSDICNV tSCKL
SCK 1 2 3 17
tSCK
18
19
tHSDO tDSDO tEN
SDO D17 D16
tSCKH tDIS
D1 D0
06973-025
Figure 35. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
Rev. 0 | Page 20 of 24
AD7984
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7984s on a 3-wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7984s is shown in Figure 36, and the corresponding timing is given in Figure 37. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO and the AD7984 enters the acquisition phase and goes into standby mode. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 18 x N clocks are required to read back the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate and consequently more AD7984s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time.
CONVERT CNV SDI CNV SDO SDI
DIGITAL HOST
SDO DATA IN
AD7984
A SCK
AD7984
B SCK
CLK
Figure 36. Chain Mode Without Busy Indicator Connection Diagram
SDIA = 0
tCYC
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSSCKCNV
SCK 1 2 3
tSCKL
16 17
tSCK
18 19 20 34 35 36
tHSCKCNV tEN
SDOA = SDIB
tSSDISCK tHSDISCK
DA17 DA16 DA15 DA1
tSCKH
DA0
tHSDO tDSDO
SDOB DB17 DB16 DB15 DB1 DB0 DA17 DA16 DA1 DA0
06973-027
Figure 37. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. 0 | Page 21 of 24
06973-026
AD7984
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7984s on a 3-wire serial interface while providing a busy indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7984s is shown in Figure 38, and the corresponding timing is given in Figure 39. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the busy indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7984 ADC labeled C in Figure 38) is driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7984 then enters the acquisition phase and goes into standby mode. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 18 x N + 1 clocks are required to read back the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and, consequently, more AD7984s in the chain, provided the digital host has an acceptable hold time.
CONVERT CNV SDI CNV SDO SDI CNV SDO SDI
DIGITAL HOST
SDO DATA IN IRQ CLK
06973-028
AD7984
A SCK
AD7984
B SCK
AD7984
C SCK
Figure 38. Chain Mode with Busy Indicator Connection Diagram
tCYC
CNV = SDIA
tCONV
CONVERSION
tACQ
ACQUISITION
ACQUISITION
tSSCKCNV
SCK 1 2 3
tSCKH
4
tSCK
17 18 19 20 21 35 36 37 38 39 53 54 55
tHSCKCNV
SDOA = SDIB
tEN
tSSDISCK
tHSDISCK
DA1
tSCKL
DA0
tDSDOSDI
DA17 DA16 DA15
SDOB = SDIC SDOC
tDSDOSDI tDSDOSDI
tHSDO tDSDO
DB17 DB16 DB15 DC17 DC16 DC15 DB1 DC1 DB0 DA17 DA16 DC0 DB17 DB16 DA1 DB1 DA0 DB0 DA17 DA16
tDSDOSDI tDSDOSDI
DA1 DA0
Figure 39. Chain Mode with Busy Indicator Serial Interface Timing
Rev. 0 | Page 22 of 24
06973-029
AD7984 APPLICATION HINTS
LAYOUT
The printed circuit board (PCB) that houses the AD7984 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7984, with its analog signals on the left side and its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7984 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7984. The AD7984 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Finally, the power supplies VDD and VIO of the AD7984 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7984 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. An example of layout following these rules is shown in Figure 40 and Figure 41.
06973-030
AD7984
Figure 40. Example Layout of the AD7984 (Top Layer)
EVALUATING THE AD7984 PERFORMANCE
Other recommended layouts for the AD7984 are outlined in the documentation of the evaluation board for the AD7984 (EVAL-AD7984CBZ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3Z.
Figure 41. Example Layout of the AD7984 (Bottom Layer)
Rev. 0 | Page 23 of 24
06973-031
AD7984 OUTLINE DIMENSIONS
3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 0.33 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8 0 0.80 0.60 0.40
10 6
1
5
5.15 4.90 4.65
SEATING PLANE
0.23 0.08
Figure 42. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
3.00 BSC SQ 0.30 0.23 0.18
6 10 *EXPOSED PAD (BOTTOM VIEW)
0.50 BSC
PIN 1 INDEX AREA 0.50 0.40 0.30
TOP VIEW
1.74 1.64 1.49
5
1
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 NOM
2.48 2.38 2.23 0.05 MAX 0.02 NOM
PIN 1 INDICATOR (R 0.19)
Figure 43. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7984BRMZ 1 AD7984BRMZ-RL71 AD7984BCPZ1 AD7984BCPZ-RL71 AD7984BCPZ-RL1 EVAL-AD7984CBZ1, 2 EVAL-CONTROL BRD3Z1, 3
1 2 3
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead QFN (LFCSP_WD) 10-Lead QFN (LFCSP_WD) 10-Lead QFN (LFCSP_WD) Evaluation Board Evaluation Board
Package Option RM-10 RM-10 CP-10-9 CP-10-9 CP-10-9
Ordering Quantity Tube, 50 Reel, 1,000 Tube, 75 Reel, 1,000 Reel, 5,000
101207-B
0.20 REF
*PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
Branding C60 C60 C60 C60 C60
Z = RoHS compliant part. This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3Z for evaluation/demonstration purposes. This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06973-0-11/07(0)
Rev. 0 | Page 24 of 24

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